Progress on adder

I have successfully synthesised a 4bit adder in VHDL using imperials VHDL course notes. Note that this isn't a simple cut and paste as quartus has or2 reserved. I have also thought abit about how to make this adder as fast as possible using carry chains.
The idea is that in a ripple adder the maximum propagation delay increases linery with an increase in the number of bits. For example quartus tells me that I have a propagation delay of 12nS with a 4bit ripple adder. Therefore a 24bit ripple adder (what will probably be in the final project) will have a delay of 72nS! limiting the circuit to a clock frequency of less than 13MHz. The higher the internal clock frequency of the modulator the greater the range of frequencies the modulator noise is spread over and therefore the better the SNR. The delay is due to the carry having to propagate from the first adder unit through all the adders until the end in a worst case.
Therefore the adder can be accelerated by computing the sum and carry of each 4bit block with AND without a carry been added to that sum. When a carry arrives at that block the result is already available without that carry having to propagate through all the gates causing the carry to be propagated at much higher speed.
This idea can be extended so that there are multiple carry chains, for example each 2bit block, each 4 and each 8 could all have a carry chain that allowed carrys to propagate rapidly along the chain.
The obvious disadvantage of using a carry chain is more than doubling the amount of logic required to implement the adder. This is not of concern for me with 18K gates to use.
Initially I plan to implement 4bit Carry look ahead units and see what kind of speed up it gives me. The adder circuit is also used also in the integrator and so any possible speed up is worth it.

the course page with loads of usefull info is here:
https://intranet.ee.ic.ac.uk/t.clarke/vhdl/

*good news! it apears the propegation delays are for worst case (IE signal traversing FPGA) so they should be alot less once I get around to actual pin placment. Hopefully delay can be low enough to run at 50MHZ (fastest oscilator on dev board).