Lets Express this graphicly

I figure a graph can explain this better. 10 iterations are run through of an input of 5 producing the red waveform. This is then run as a PWL source in simetrix to simulate a bit stream output @ 2MHz sample rate. This output is then filtered by an low pass RC filter with f -3dB = 20KHz. As can be observed the (green) output is the input code (66% full scale) with some modulator noise.
The modulator noise can be reduced by increasing the bits of the modulator (not applicable for creating a switching amp), increasing the oversample ratio (increasing freq sample) or by increasing the order of the modulator. Or any of those in combination.

Dirty Pascall done

This is a very dirty pascal program that just shows what I intend to do is actually possible. The input word is (equivalent to) 5bits 2's compliment with D5 the sign bit; as this program is a model I have only got base 10 input so values from -16 to 16 are acceptable. The more iterations the higher the sample rate and so the lower the noise of the modulator.
So for example if you input 0 and perform 10 iterations the output is:
0101010101
Therefore the mean is 0.5, taking into account that 0 is actually 1/2 full scale (as the modulator accepts negative inputs) this means the mean output is 0.

//This simulates a digital delta sigma modulator with a 5bit input
program deltasigma;

var
input, sum, int, comp, QN: double;
loop, endeth: integer;

begin
writeln('Input the base 10 value of the input voltage (max 16) (min -16): ');
read(input);
writeln('Itarations? ');
read(endeth);

//intial conditions
comp := 0;
QN := 0;
int := 0;
sum := 0;

for loop := 1 to endeth do begin
sum := (input + QN);
int := (int + sum);
if int > 0 then
comp := 1;
if int < 0 then
comp := 0;
if int = 0 then
comp := 0;
if comp = 0 then
QN := 16;
if comp = 1 then
QN := -16;
writeln(comp);
end;
end.

1st p0st

I have had an awesome idea for an amplifier that has no analog amplification and uses only switching waveforms and therefore is very efficient!

Diagram:
usb uart > I2S > fpga based delta sigma modulator > bitstream > gate drive > power fets

The delta sigma modulator will probably initially take 24bit input with unused LSB's dithered using a pseudo random generator. The modulator will initially be of second order and operate with a sample rate of 3MHz. This is to simplify the mathematics of the design as 2nd order should be stable! also sample rate is ultimately constrained by gate capacitance of the power fets.

To verify that this will work I shall code a simulation of the delta sigma modulator in PASCAL. As a digital circuit will behave ideally I can also do some fft on a suitably low pass filtered version of the bitsteam output and check that performance is adequate!